The present disclosure relates generally to electronic devices, and more particularly, to synchronous bus driving techniques of such devices.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Electronic systems or components may typically implement a synchronous bus to interconnect multiple devices according to a clock signal. As technology advances, electronic systems may interconnect an increasing number of electronic devices via the synchronous bus. For example, a liquid crystal display (LCD) is commonly used as a screen or a display for a wide variety of electronic devices. Such LCD devices typically include thousands (or millions) of picture elements, i.e., pixels, arranged in a matrix of rows (also referred to as “scanning lines” and columns (also referred to as “data lines”). For any given pixel, the amount of light viewable on the LCD depends on the voltage driven to the pixel. The pixels may be driven by scanning line and data line circuitry which converts digital image data into analog voltage values which may be supplied to pixels. The driving circuitry may drive the pixels using clock signals and data signals received from a display controller via a synchronous bus.
To meet demands for larger display areas, LCD devices may include a large matrix of pixels. To synchronously drive such a large pixel matrix, data signals and clock signals may be transmitted via a relatively long synchronous bus to interconnect all the data lines of the pixel matrix. Due to resistive-capacitive (RC) characteristics and/or electromagnetic interferences of the bus, signals may increasingly degrade as they are transmitted through the length of the bus. For example, a clock signal may generally be a square wave having steep edges, and data may be latched according to the rising and/or falling edges if the clock signal. However, a clock signal that is transmitted through a long bus may become degraded due to the RC effects, and may have a sloped, rather than a square waveform. The sloped waveform of a degraded clock signal may cause data to be latched later, or not at all.